For enhancing quality standards and productivity in the semiconductor industry, not only implementation of improved technologies resulting from research and development efforts but also unrelated efforts in the areas of design, validation and engineering that may ensure a good test coverage in the shortest time are needed to meet time to market targets and reduce costs. The speeding up of the industrialization phase and optimizing test strategy for timely achieving validation and qualification of devices involves several factors such as the choice of the testing platform and of the level of test coverage, built-in self-tests, device settings and repair techniques. To achieve the most effective results the best compromise must be made between added costs in terms of silicon area, HW/SW development time and relative costs, testing time and test coverage.
Regarding testing of Flash Memory Devices, fundamental testing phases in a Flash Memory fabrication process are described below. Electric Wafer Sort (EWS) is an electrical test performed on each device at wafer level. During this test, parametric measurements and functionality checks are executed to validate reliability. Moreover the setting of internal registers and trimming of internal references (Reference Cells for the write and read operations, voltage and current internal reference: Bgap, Iref) is performed to enhance performance, considering possible deviation of parameters due to the process stability (process spreads). During this testing flow it is possible to detect and substitute the fail locations of the memory array with spare array elements. During this testing flow speed conditions are not aggressive in terms of test frequency also because of the probe cards that are used to couple the tester to the device pads.
Final or Package Test (FT) performed on assembled parts executing parametric and functionality checks at the specification limits with the intent of classifying devices in terms of features and quality. This testing phase is to a large extent executed in user mode interfacing. Electrical Wafer Sort is a sequence of test routines carried out on the wafer before and after a baking step, according to the following flow.

EWS1—During this first part of the test sequence, the Flash Memories fabricated on the wafer are UV erased, parametric and functionality tests are performed to check the efficiency and to expose possible failures mechanisms also by electrical stressing (the devices for accelerating possible failure mechanisms). Setting of internal references and registers is also performed at this level. Bake—The wafer is placed in an oven at 250° C. for 24 hours. EWS2—During this part of the test sequence, retention checks are performed to verify if any significant charge loss has occurred to memory cells following the accelerated stress of the baking. Inking—Failed dices are marked by inking to discriminate good dices, at assembly level.
The tests performed during EWS can be classified in groups described as follow. Parametric Tests: to verify open circuits, short circuits or current leakage on pins, power consumption. Setting or Trimming Tests: to set and verify configuration of internal registers and of reference cells. Functional Tests: to verify the correct functionality of the device at life time zero for standard operations such as programming, erasing and reading. Reliability Tests: to detect and highlight possible defects in memory array or in the circuitry that may compromise quality of the device. Redundancy Analysis and Repair: some defects are repairable within certain limits depending on device architecture, by using purposely integrated spare elements.
Developing and debugging the software of an EWS flow for a new device to be manufactured is a time consuming and relatively costly job. Testing machines are also expensive. Both the software and the testing hardware have a cost that is commensurate to the complexity and numerosity of tests that must be performed according to the EWS flow to achieve the acceptable reliability. In case of memory devices, the impact that a single routine has on the global time requested to fully test a device depends to a large measure to the size of the memory array.
In the case of memory devices, the main test routines that may be executed via built-in testing are described below. Parallel (double or tetra word) programming using User Mode (UM) or TM through defined accelerator pin. Configuration and redundancy internal register setting, Reference Cell Setting, UM & TM Read pattern (diagonal, CK and CKN), UM & TM Program pattern (diagonal, CK and CKN), Redundancy analysis and Repair, Vgmax and Vgmin search algorithms.